1. Field of the Invention
The present invention pertains to a structure and method for reducing or preventing junction spiking due to silicon diffusion through a wall surface of an overetched contact via formed in a silicon substrate.
2. Brief Description of the Background Art
In the fabrication of multi-layered semiconductor devices, it is common to have a single-crystal silicon substrate with a dielectric layer overlying the silicon substrate. Electrical contacts may be formed by creating an opening through the dielectric layer to the surface of the silicon substrate. The opening is subsequently filled with a conductive material, which is typically a metal such as aluminum or copper.
One of the preferred methods of producing the opening (i.e., contact via) through the dielectric layer to the surface of the silicon substrate is by plasma etching through a mask on the surface of the dielectric layer. Variance occurs in this etching process and some degree of overetch into the silicon substrate is necessary to ensure that the contact is completely open (i.e., there is no dielectric material remaining between the metal contact and the silicon substrate). The degree of overetch will vary with overall pattern factors and geometric considerations.
Conventional integrated circuit processing steps can cause silicon atoms to diffuse from single-crystal silicon into a contact of pure aluminum or pure copper adjacent to the single-crystal silicon. When the diffusion is sufficient to short out a shallow p-n junction in the silicon, this phenomenon is known as junction spiking.
In order to prevent such junction spiking, a diffusion barrier layer is typically applied over the internal surface of the contact via after etching of the opening through the dielectric layer. One of the preferred methods of application of the diffusion barrier layer is by physical vapor deposition (PVD), in particular, high density plasma sputter deposition. The use of high density plasma sputtering techniques results in the deposition of diffusion barrier layers having excellent barrier properties, even in difficult-to-fill small feature size contact vias. However, even when diffusion barrier layers are deposited using high density plasma sputtering techniques, junction spiking of contacts is still occasionally observed.
Therefore, it would be desirable to provide a new device microstructure and method of forming the structure which would reduce or prevent junction spiking due to silicon diffusion through a wall surface of an overetched contact via.
We have discovered a new semiconductor contact microstructure and a method of forming the structure which reduces junction spiking in semiconductor contact vias. The structure is applicable when the contact via has a three-dimensional shape which makes it difficult to apply a diffusion barrier layer in the area adjacent the interface between a silicon surface and a metal such as aluminum or copper.
In particular, the semiconductor contact microstructure comprises a feature which includes a silicon base and at least one sidewall extending upward from the silicon base. The sidewall includes a silicon portion in contact with the silicon base. Typically the height of the silicon portion of the sidewall above the silicon base is less than about 0.5 xcexcm. The sidewall also includes at least one portion which comprises a first dielectric material which is in contact with (and typically extends upward from) the silicon portion of the sidewall. Overlying at least the silicon portion of the sidewall is a layer of a second dielectric material, preferably silicon oxide. In most applications, a diffusion barrier layer overlies the silicon base, the layer of second dielectric material, and at least part of the sidewall portion which is comprised of the first dielectric material. Typically, the first and second dielectric materials are both silicon oxide, although the first dielectric material may be a low k dielectric, while the second dielectric material may be silicon oxide.
The method comprises the steps of. providing a semiconductor device feature which includes a silicon base and at least one sidewall extending upward from the silicon base, where the sidewall includes at least one silicon portion in contact with the silicon base, and another portion comprising a first dielectric material which is in contact with the silicon portion of the sidewall; and, creating a layer of a second dielectric material, preferably silicon oxide, over the at least one silicon sidewall portion. The method may also include subsequent steps of sputter etching to remove dielectric material from the surface of the silicon base; and, applying a diffusion barrier material over the silicon base, the layer of second dielectric material, and at least a portion of the sidewall comprising the first dielectric material.
The method of the invention is particularly effective when used to prepare electrical contacts having a feature size of less than about 0.5 xcexcm and an aspect ratio of greater than about 2:1.
The method of the invention greatly reduces or eliminates junction spiking at the bottom of contact vias when the via has been overetched, leaving via sidewalls exposed at the bottom of the contact which comprise silicon. Application of a dielectric layer, such as silicon oxide, over the portion of the via wall surface which comprises silicon, followed by removal of any excess dielectric formed upon the bottom surface of the via, and subsequent application of a diffusion barrier layer over the interior of the via surface, reduces the possibility of junction spiking after filling of the via with a conductive metal, such as aluminum or copper. The presence of the dielectric material on the silicon sidewall of the via is effective to protect this portion of the sidewall from diffusion into the conductive metal with subsequent current leakage.